The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device with circuits for distributing the power dip generated during a burn-in test.
Typically, a burn-in test is performed on all electronic components to stabilize performance characteristics, and identify defects or stress failures. This is certainly true of semiconductor devices. However, the simultaneous fabrication of many semiconductor devices on a single silicon wafer creates additional challenges to the performance of burn-in testing. In fact, the burn-in test of semiconductor devices is usually performed as part of the packaging step. A such it is impossible to repair any defects found during testing. This result is increased manufacturing cost and time.
In a semiconductor memory device such as dynamic random access memory (DRAM), most of the defects found relate to single bit defects which require a lengthy test time to identify. The single bit defect may be caused, for example, by defects in the gate oxide layer of a transfer gate, or the junction between the dielectric layer of a storage capacitor and the storage node. Any one of these exemplary problems will cause current leakage such that the memory cell must be deemed defective.
Conventionally, when performing an initial burn-in test on a 64 Mbit DRAM, a single word line is selected for every 4096 or 8192 cycles. Thus, the efficiency in applying a stress voltage to the all memory cells is low. In order to improve such efficiency as well as to reduce the burn-in test time, a method has previously been proposed wherein all word lines are simultaneously selected while the semiconductor devices are yet in the wafer state. This may improve the yield rate, reducing the overall production cost. However, if all the word lines (for example, the main and section word lines of DRAM) are simultaneously activated, a high charge consumption is required, so that it takes a long time to set the section word lines to the required voltage level.
In order to resolve this problem, all the main word lines are first selected, and then the section word lines are properly divided to be sequentially activated according to an address coding. However, this process also suffers from a drawback in which the power line is subjected to a large load because simultaneous activation of the main word lines requires a large amount of power. This is increasingly true as integration of DRAM increases.
Finally the conventional solution may result in damage to the power line. Although this result may be avoided by increasing the area of the power line, such remedy increases chip size. Moreover, it is not economical to increase the area of the power line simply to perform a burn-in test.